Modern semiconductor circuits employ memory assemblies with large memory capacity, which are frequently embedded in the respective semiconductor circuit. It is desirable for memory assemblies to have high access speed, lower supply voltage, and lower power consumption or energy consumption. As a result, memory assemblies typically are optimized with regard to access speed, space requirement, and dynamic and static power consumption.
A typical six transistor (6T) memory cell has a relatively high leakage current. In addition the space requirement of a typical 6T memory cell is relatively high. Alternative memory cells, which have a lower space requirement than the typical 6T memory cell, normally are refreshed and mostly have a greater access time than the typical 6T memory cell. For example, a three transistor (3T) cell, which is an alternative conventional memory cell with a large capacity, typically employs separate metal lines for reading and writing and for the supply voltage. Alternatively, the port for the read and write word line can be connected on the 3T memory cell, however, this results in some disadvantages for the 3T memory cell.
Therefore, it would be desirable for a memory cell to have a low space requirement, a short access time, and low power consumption, as well as needing only a low supply voltage. Furthermore, a need exists for a read device which has a low space requirement and low power consumption, as well as needing only a low supply voltage.
For these and other reasons, there is a need for the present invention.